Integrated circuits (ICs) use metal lines to connect the various circuit elements together. These lines are called interconnect structures.
Because a high density of circuit elements and connections is required, it is necessary to use several levels of metal levels.
Each level contains a planar structure of metal lines, with layers of an insulator such as silicon dioxide used to separate the levels from one another.
It is necessary to interconnect the layers to one another, to enable current to flow between the layers. These interconnections are called vias.
Vias are located in small holes formed in the insulator. These holes are filled with a metal to form an interconnection between metal lines in different levels.
One type of via is for example a Through Silicon Via (TSV) etched through a silicon substrate (or wafer), to interconnect with another wafer. Those TSVs are useful in 3-dimensional stacking of integrated circuits (or chips), avoiding the use of external wiring bonding.
Unfortunately, variations in processing parameters, such as a deviation from a specified pressure, current, chemical composition or amount of additives of, e.g., the plating solution, and/or temperature while the via is being filled with metal, may lead to the formation of embedded voids (completely surrounded by the metal in the via) within the via.
Furthermore, embedded voids may similarly occur in other recessed regions (or recesses) such as trenches and contact structures in or on a substrate (or wafer) while these recesses are filled with a material.
Embedded voids are a site of potential future failure of the integrated circuit, compromising the performance of the device being manufactured.
Therefore, currently, a lot of attention is being given to the development of void free structures formed in or on a semiconductor substrate.
However, embedded voids are virtually impossible to detect by non-destructive defect inspection methods known in the art, such as optical or scanning electron microscope (SEM) surface inspection.
The known methods commonly available for finding and evaluating embedded voids, such as SEM or Transmission Electron Microscopy (TEM) in conjunction with cross-sectioning (i.e., cross sectional TEM or SEM) or with a focused ion beam, have the disadvantages of being destructive, requiring at least local destruction of the substrate (or wafer) under test, and are time-consuming and costly.
In performing for example a SEM sectioning method for detecting embedded voids in a wafer, a sample wafer is broken, or a focused ion beam is used to cut away material, exposing a side view of the via. The SEM can then image the via. This method has limitations of being destructive and slow (and is therefore limited to post-analysis of failures).
Cross sectional TEM is also a way of finding and evaluating embedded voids but having the disadvantage that it is a destructive method as well.
A non-destructive method like X-Ray Tomography (XRT) is also possible to be performed for finding and evaluating embedded voids, but this method has the disadvantage to only work for small samples, and not on the whole (or entire) substrate (or wafer).
Furthermore the measurement time with XRT can be hours, for example more than 12 hours for a single Through Silicon Via.
As such, these methods are not suitable for in-line monitoring of embedded voids present in a structure formed in or on a semiconductor substrate.
Therefore, the detection of the presence (or absence) of embedded voids in structures formed in or on a semiconductor substrate remains a challenging problem.